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Freescale Semiconductor

Data Sheet

Document Number: MSC8144

Rev. 16, 5/2010

MSC8144

FC-PBGA–783

29 mm × 29 mm

Quad Core Digital Signal

Processor

? Four StarCore ? SC3400 DSP subsystems, each with an SC3400

DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,

memory management unit (MMU), extended programmable

interrupt controller (EPIC), two general-purpose 32-bit timers,

debug and profiling support, and low-power Wait and Stop

processing modes.

? Chip-level arbitration and system (CLASS) that provides full

– The two Ethernet controllers support 10/100/1000 Mbps

operations via MII/RMII/SMII/RGMII/SGMII and the SGMII

protocol using a 4-pin SerDes interface at 1000 Mbps data rate

only.

– The ATM controller supports UTOPIA level II 8/16 bits at

25/50 MHz in UTOPIA/POS mode with adaptation layer

support AAL0, AAL2, and AAL5.

fabric non-blocking arbitration between the processing elements

and other initiators and the M2 memory, DDR SRAM controller,

device configuration control and status registers, and other

targets.

? 128 Kbyte L2 shared instruction cache.

? 512 Kbyte M2 memory for critical data and temporary data

buffering.

? 10 Mbyte 128-bit wide M3 memory.

? 96 Kbyte boot ROM.

? Three input clocks (shared, global, and differential).

? Four PLLs (system, core, global, and serial RapidIO).

? DDR controller with up to a 200 MHz clock (400 MHz data rate),

16/32 bit data bus, supporting up to 1 Gbyte in up to two banks

and support for DDR1 and DDR2.

? DMA controller with 16 bidirectional channels with up to 1024

buffer descriptors, and programmable priority, buffer, and

multiplexing configuration.

? Up to eight independent TDM modules with programmable word

size (2, 4, 8, or 16-bit), hardware-base A-law/ μ -law conversion,

up to 128 Mbps data rate for all channels, with glueless interface

to E1 or T1 framers, and can interface with H-MVIP/H.110

devices, TSI, and codecs such as AC-97.

PCI designed to comply with the PCI specification revision 2.2 at

33 MHz or 66 MHz with access to all PCI address spaces.

Serial RapidIO? 1x/4x endpoint corresponds to Specification 1.2

of the RapidIO trade association, and supports read, write,

messages, doorbells, and maintenance accesses in inbound mode,

and messages and doorbells in outbound mode.

I/O interrupt concentrator consolidates all chip maskable interrupt

and non-maskable interrupt sources and routes them to

INT_OUT, NMI_OUT, and the cores.

UART that permits full-duplex operation with a bit rate of up to

6.25 Mbps.

Serial peripheral interface (SPI).

Four timer modules, each with four configurable16-bit timers.

Four software watchdog timer (SWT) modules.

Up to 32 general-purpose input/output (GPIO) ports, 16 of which

can be configured as maskable interrupt inputs.

I 2 C interface that allows booting from EEPROM devices.

Eight programmable hardware semaphores.

Thirty two virtual maskable interrupts and one virtual NMI that

can be generated by a simple write access.

Optional booting via serial RapidIO port, PCI, I 2 C, SPI, or

Ethernet interfaces.

? QUICC Engine? technology subsystem with dual RISC

processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction

RAM, supporting three communication controllers with one ATM

and two Gigabit Ethernet interfaces, to offload scheduling tasks

from the DSP cores.

? 2007–2010 Freescale Semiconductor, Inc.

Note:

This document supports mask set M31H.

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